(1) Field of the Invention
The present invention relates to a method used to fabricate a dynamic random access memory, (DRAM), device, and more specifically to a method used to create a crown shaped capacitor structure, for the DRAM device.
(2) Description of the Prior Art
Device performance and cost reductions are the major objectives of the semiconductor industry. These objectives have been in part realized by the ability of the semiconductor industry to produce chips with sub-micron features, or micro-miniaturization. Smaller features allow the reduction in performance degrading capacitances and resistances to be realized. In addition smaller features result in a smaller chip, however still possessing the same level of integration obtained for semiconductor chips fabricated with larger features. This allows a greater number of the denser, smaller chips to be obtained from a specific size starting substrate, thus resulting in a lower manufacturing cost for an individual chip.
The use of smaller features, when used for the fabrication of dynamic random access memory, (DRAM), devices, in which the capacitor of the DRAM device is a stacked capacitor, (STC), structure, presents difficulties when attempting to increase STC capacitance. A DRAM cell is usually comprised of the STC structure, overlying a transfer gate transistor, and connected to the source of a source/drain of the transfer gate transistor. However the decreasing size of the transfer gate transistor, limits the dimensions of the STC structure. To increase the capacitance of the STC structure, comprised of two electrodes, separated by a dielectric layer, either the thickness of the dielectric layer has to be decreased, or the area of the capacitor has to be increased. The reduction in dielectric thickness is limited by increasing reliability and yield risks, encountered with ultra thin dielectric layers. In addition the area of the STC structure is limited by the area of the underlying transfer gate transistor dimensions. The advancement of the DRAM technology to densities of 256 million cells per chip, or greater, has resulted in a specific cell in which a smaller transfer gate transistor is being used, resulting in less of an overlying area for placement of overlying STC structures.
Two methods that can be used to increase STC capacitance, while still decreasing the lateral dimension of the capacitor, are the use of rough, or hemispherical grain (HSG), silicon layers, and the use of crown shaped capacitor structures. First, referring to the crown shaped capacitor structures, the creation of a polysilicon, or amorphous silicon, storage node structure, comprised of both vertical and horizontal silicon features, results in a greater electrode surface area than counterparts fabricated without vertical features. Secondly the use of an HSG silicon layer, comprised of convex and concave features, and used for the top layer of the storage node structure, again results in a greater degree of surface area than counterparts fabricated with smooth silicon layers. Therefore the combination of a crown shaped capacitor structure, comprised with a top layer of HSG silicon, residing on the crown shaped storage node structure, is an attractive option for high density DRAM devices.
The integration of a crown shaped storage node, and an overlying HSG silicon layer, can result in less than desirable results due to the selectivity needed between the HSG silicon layer, and the adjacent isolation regions, as well as the ability to create a capacitor dielectric layer at an HSG silicon-isolation interface, or corner. A silicon nitride layer, used for isolation between capacitor structures, as well as for an etch stop layer during an oxide recess procedure, is usually present between amorphous silicon, crown shaped structures, during the selective formation of an HSG silicon layer on the amorphous silicon, crown shaped storage node structure. However increased selectivity can be achieved, if a silicon oxide layer were used, in place of silicon nitride, between capacitor structures, thus improving DRAM device yield. This invention will offer a novel procedure for forming crown shaped storage node structures, featuring greater selectivity for HSG silicon formation, via use of an undoped silicon oxide isolation layer. In addition this invention will offer an improved procedure, for forming a nitride - oxide capacitor dielectric layer, specifically at the interface, or at a corner, in which the vertical feature of the crown shaped structure, comprised with an outer layer of HSG silicon, interfaces the isolation layer. Conventional procedures offer the HSG silicon layer directly interfacing the isolation region. However with this invention, the removal of the undoped silicon oxide layer, post HSG silicon formation, present a smooth, non-HSG silicon surface, at the corner between the vertical feature of the crown shaped structure and the isolation region, offering an interface, more conducive to subsequent capacitor dielectric formation. Prior art, such as Tseng, in U.S. Pat. No. 5,716,883, describes a fabrication method for a crown shaped capacitor structure, while Lou, et al, in U.S. Pat. No. 5,597,754, describe a method for forming an HSG silicon layer, for a DRAM storage node structure. However none of the prior art describe the process used in the present invention, in which a disposable silicon oxide layer is used as an isolation region, between capacitor structure, thus increasing the selectivity between HSG silicon, and the isolation layer, nor does the prior art describe a post - HSG silicon, disposable silicon oxide layer, resulting in a corner, comprised of a vertical feature of the crown shaped structure, and the isolation region, more conducive to the formation of a capacitor dielectric layer.